This disclosure relates generally to input/output (I/O) buses used to interconnect peripheral devices in computing systems, and more specifically, to re-routing lane signals from faulty signal carriers to existing and healthy signal carriers.
A Peripheral Component Interconnect Express (PCIe) bus is a high performance I/O standard serial bus that interconnects endpoints. A point-to-point physical connection between two PCIe endpoints (e.g., Ethernet, USB, graphics devices, etc.) is called a link. A link is used to transfer I/O data serially in packets. The PCIe link may include one or more signal lines called lanes. A single lane may include two pairs of signal carriers (e.g., fiber, wire, etc.) for transmitting respective differentiating lane signals. One lane signal (or differentiating pair of lane signals) may be utilized for receiving data and one differential pair of lane signals may be utilized for transmitting data. Each differential pair of lane signals may be capable of transmitting or receiving data one bit at a time. A link consisting of one lane is called an x1 link, and has a link width of one lane. A link consisting of two lanes is called an x2 link, and has a link width of two lanes. PCIe specifications may allow for link widths of x1, x2, x4, x8, and x16 lanes. During a process called “link training,” two peripheral devices may negotiate link parameters. For example, the devices may determine link width capacity (e.g., bandwidth), link speed, lane polarity, etc.